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1 features ? two pcm codecs (itu-t g.711/g.712, 8khz pcm) ? four audio tx/rx interfaces ? single 3.3v power supply ? flexible voice data port works in st-bus, gci and ssi modes ? serial microport interface compatible with motorola and national semiconductor ? low external component count ? low power (43mw typical) ? power-down mode ? differential microphone inputs ? programmable bias voltage output for electret microphones ? microphone presence detection ? microphone mute ? programmable microphone gain (0db to +46.5db in 1.5db steps) ? itu-t g.712 high-pass and low-pass tx filtering ? programmable sidetone gain (-39db to +6db in 3db steps) ? sidetone mute ? differential earpiece driver outputs ? 66mw rms into 32 ohms ? 150mw rms into 16 ohms ? programmable earpiece gain (-28db to +2db in 2db steps) ? programmable rx volume control (-21db to 0db in 3db steps) ? rx channel mute ? itu-t g.712 low-pass rx filtering ? programmable/optional rx hi-pass filter (6 corner frequencies in range 40hz-400hz) ? three pcm data formats - 16-bit linear, companded itu-t a-law or u-law ? cross-point connects pcm channels to any of the four audio tx/rx interfaces ? auxiliary ringing/announcement input (to loud speaker outputs) applications ? digital telephone sets ? voip enterprise telephones ds5320 issue 3 june 2002 ordering information mt92303/pr 44 pin mqfp -40 to +85 c figure 1 - block diagram 4 4 pll serial microport interface g.712 codec #1 crosspoint g.712 codec #0 pcm voice interface vref audio interface #3 audio interface #2 audio interface #1 audio interface #0 auxtone ear mic bias micdet resetb ear mic bias micdet ear mic ear/speaker mic bias sysclk mt92303 3.3v quad interface, dual codec advance information
mt92303 advance information 2 figure 2 - pin diagram pin description pin # name type description system 5 sysclk input master clock (2.048, 4.096, 10.24, 20.0, 20.48, 25.0 or 50.0mhz) 12 resetb input active low reset signal for digital circuitry 6 vddd power vdd for digital circuitry and pll 7 gndd ground gnd for digital circuitry and pll pcm interface 4 c4i /dcl/sck input serial clock: st-bus = 4.096mhz, gci = 1.536 - 4.096mhz ssi = 0.512 - 4.096mhz 3 f0i/fsc/sc2 input frame alignment. st-bus active low pulse, gci active high pulse, ssi active high 2 dsti/d in /srd input serial data 1 dsto/d out /std output serial data serial microport 11 cs input enables serial microport. active low. rising edge completes the cycle. 10 sclk input data clock for serial microport 9 data1 output motorola/national mode: output. 8 data2 input motorola/national mode: input. analog 24 vref output on-chip voltage-reference decoupling capacitor, 100nf to gnda 29 vdda power vdd for analog circuitry 28 gnda ground gnd for analog circuitry 27 sub ground chip substrate (connect to gnda) 3 9 4 4 4 3 4 2 4 1 4 0 3 8 3 7 3 6 3 5 3 4 1 2 3 4 5 6 7 8 9 10 33 32 31 30 29 28 27 26 25 24 1 7 1 2 1 3 1 4 1 5 1 6 1 8 1 9 2 0 2 1 2 2 11 23 ear1p ear1n gndp1 auxtone vdda gnda sub mic1p mic1n vref micon v d d p 0 s p e a k e r n s p e a k e r p g n d p 0 v d d p 3 e a r 3 p e a r 3 n g n d p 3 2 e a r 2 p e a r 2 n v d d p 2 1 r e s e t b m i c b i a s 3 m i c d e t e c t 3 m i c 3 p m i c 3 n m i c b i a s 2 m i c d e t e c t 2 m i c 2 p m i c 2 n m i c b i a s 0 m i c 0 p dsto/d out /std dsti/d in /srd f0i/ fsc/sc2 c4i /dcl/sck sysclk vddd gndd data2 data1 sclk cs 44 pin mqfp
advance information mt92303 3 audio interface #3 13 micbias3 output programmable voltage (0 to 2.5v in 15 steps) for electret microphones 14 micdetect3 input comparator input to detect presence & muting of microphone 15 mic3p input positive microphone input 16 mic3n input negative microphone input 40 vddp3 power vdd for rx analog o/p circuitry (audio interface #3) 39 ear3p output positive earpiece output 38 ear3n output negative earpiece output 37 gndp32 ground gnd for rx analog o/p circuitry (audio interfaces #3 & #2) audio interface #2 17 micbias2 output programmable voltage (0 to 2.5v in 15 steps) for electret microphones 18 micdetect2 input comparator input to detect presence & muting of microphone 19 mic2p input positive microphone input 20 mic2n input negative microphone input 36 ear2p output positive earpiece output 35 ear2n output negative earpiece output 34 vddp21 power vdd for rx analog o/p circuitry (audio interfaces #2 & #1) audio interface #1 26 mic1p input positive microphone input 25 mic1n input negative microphone input 33 ear1p output positive earpiece output 32 ear1n output negative earpiece output 31 gndp1 ground gnd for rx analog o/p circuitry (audio interface #1) audio interface #0 21 micbias0 output programmable voltage (0 to 2.5v in 15 steps) for electret microphones 22 mic0p input positive microphone input 23 mic0n input negative microphone input 44 vddp0 power vdd for rx analog o/p circuitry (audio interface #0) 43 ear0n/speakern output negative earpiece output (high power for loud speaker) 42 ear0p/speakerp output positive earpiece output (high power for loud speaker) 41 gndp0 ground gnd for rx analog o/p circuitry (audio interface #0) auxiliary tone input 30 auxtone input auxiliary ringing/announcement input (to loud speaker outputs) pin description (continued)
mt92303 advance information 4 functional description the mt92303 dual codec provides complete audio to pcm interfaces including filtering and optional data companding as required by the itu-t g.711 & g.712 recommendations. programmable gain allows adjustment for a wide range of transducer sensitivities - two microphone amplifiers and four earpiece amplifiers are provided to allow connection to a handset, headset, auxiliary channel and microphone/speaker. a cross- point circuit allows either codec to be connected to any of the four audio interfaces. programmable voltage sources are available for electret biasing on the microphone channels. pcm voice data is passed via a serial interface which operates in st-bus, gci or ssi mode. st-bus mode allows the codecs to be allocated to any of the 32 available channels. control and programming of the codecs is carried out over a flexible, serial, micro-controller interface. figure 3 - block diagram mic detect electret bias u/a law u/a law g.712 filtering sidetone cross-point voice serial pcm interface control for companding mode, rx gain control(s), sidetone level, rx hi-pass filter, cross-point, muting, electret biasing, microphone pre-amp and gain, pll 4 serial uport 4 d a c a d c u/a law u/a law g.712 filtering sidetone d a c a d c mic detect electret bias electret bias vref pll sysclk vref resetb auxtone codec #1 codec #0 data data data data status
advance information mt92303 5 voice channel figure 4 shows the companding, filtering and gain stages in a single voice channel as set up by the cross-point. the rx channel (top) and tx channel (bottom) both use a mixture of digital-dsp and analog techniques. the dsp domain is towards the left of the diagram and extends from the pcm interface to the dac and adc blocks. rx channel pcm data is taken in either linear or companded form and is processed by the dsp circuitry. this provides a digital volume control, an access point for sidetone, and the multi-order low-pass filtering required to remove the sampling aliases in the digitized data. the 6 th order low-pass filter response is shown in figure 5. an optional 1 st order high-pass filter is also provided. in addition to the gain adjustment, the rx dsp channel may also be turned-off (?muted?). the filtered version of the data is converted to an analog signal by the dac and continuous- time low-pass filter before passing through the cross-point circuitry to the variable-gain output buffer. the buffer provides a differential output signal which allows near rail-to-rail operation and can deliver 66mw into a 32 ohm load. as shown in figure 4, the rx gain may be adjusted in two places. the ?dsp? provides adjustment from -21db to +0db in 3db steps, and the ?analog? from -28db to +2db in 2db steps. figure 4 - single voice-channel dsp and analog circuitry figure 5 - rx low-pass filter response adc dac -21db to 0db in 3db steps bypass control 8/16 u/a law smoothing filter -28db to +2db in 2db steps rec 0.90vrms @ 0dbm0 cross point bypass control 8/16 u/a law g.712 filtering 6th order low-pass @ 3.4khz 4th order hi-pass @ 150hz anti-alias filter 0db to 22.5db in 1.5db steps mic 0.611vrms @ 0dbm0 24db bypass control pre-amp sidetone -39db to +6db in 3db steps g.712 filtering 6 th order low-pass @ 3.4khz 1 st order hi-pass @ 0-400hz cross point ?dsp? ?analog? rx tx 0db -3db -2db -1db 1khz 2khz 3khz
mt92303 advance information 6 loud speaker drive the mt92303 provides four audio interfaces, all of which provide the same gain adjustments and output drive voltage levels. however, audio interface #0 has an output buffer which is capable of delivering more current than the others, and is intended for use with a loud speaker. this output can drive 150mw r.m.s. into a 16 ohm load - this represents almost rail-to-rail operation from the ?bridge? configured outputs. the four buffers each have the same output resistance - typically 1 ohm. other loud speaker impedances may be used (as long as they are greater than or equal to 16 ohms) and will allow a power output (t.h.d. < 1%) of: ? power = 150mw x 16 / rload the mt92303 can be used with loud speaker impedances below 16 ohms, but should not be allowed to provide extra drive current by doing this. the loud speaker driver is designed to deliver sufficient current to maintain a maximum amplitude signal across a 16 ohm load - exceeding this current may cause long-term damage to the device. if impedances below 16 ohms are used, then the ?rx analog gain? should not be set to maximum. for example, an 8 ohm loud speaker should be used with gains which are at least 6db below the maximum. it should be noted that in this example, the electrical power delivered to the 8 ohm load is less than that delivered to a 16 ohm load at maximum gain. tx channel an optional pre-amp and a variable gain stage provide a very large range of gain adjustment for the microphone signal. the boosted signal is passed through an anti-alias filter before it is digitized by the adc and routed to the dsp circuitry. the dsp band-pass filtering provides a sharp cut-off above 3.4khz to prevent aliasing by the 8khz sampling, and also provides a high-pass function at 150hz to remove low-frequency voice energy. as shown in figure 4, the pre-amp and variable gain block combine to allow the tx gain to be adjusted from 0db to +46.5db in 1.5db steps. figure 6 - tx band-pass filter response the 8khz samples are available in either 16-bit linear form, or 8-bit u-law or a-law companded form. the differential amplifiers may be used with electret microphones as shown in figure 8, or with dynamic microphones which have no bias requirements. even though they require no d.c. biasing, dynamic microphones must still be connected to the chip inputs with a coupling capacitor. dc offset voltages which potentially exist on the amplifier inputs are automatically cancelled by a sequence which runs each time the circuit is powered-up (see section ?automatic dc offset cancellation?). 0db -3db -2db -1db 1khz 2khz 3khz
advance information mt92303 7 the ?mic? inputs of the tx channel have a differential input impedance which is sufficiently high to allow the use of small value coupling capacitors. the input impedance is formed by the internal gain-setting resistors which are used around the op-amps, and consequently the value of the input impedance is dependent on the selected gain as shown in table1. table 1 - microphone input impedance automatic dc offset cancellation (tx) the amplifiers in the tx channel can provide gains as high as 46.5db (linear gain of x211). potential dc input offset voltages on the amplifier inputs need to be controlled so that they do not affect the dynamic range of the channel. these dc offset voltages are removed by a sequence which automatically runs each time the tx ?analog? circuitry is enabled/powered-up (see control register ?audio interface: enable?). the ?offset cancellation? routine works by using internal dacs to introduce small correction voltages into the amplifiers so that their outputs have a nominal dc level of 0v (measured differentially). the digital portion of this auto calibration circuitry is clocked by the ? frame alignment? input and requires up to 128 clock pulses. it is important that the on-chip voltage reference is powered-up and allowed to settle before the ?offset cancellation? is initiated (by enabling the tx ?analog? circuitry). there are two tx ?analog? channels, each of which has its own ?offset cancellation? circuitry. these can operate completely independently of each other if required. it is recommended that the programming sequence used for the mt92303 is arranged such that the ?offset cancellation? routine is run each time a new ?call? is setup. in this way, the offset correction will be able to track any ?drift? in operation of the mt92303 over its lifetime. sidetone path the dsp circuitry provides a path between the tx and rx channels for the adjustment of sidetone level. in addition to the large range of adjustment, the sidetone may also be turned-off (?muted?). as shown in figure 4, the sidetone gain may be adjusted from -39db to +6db in 3db steps. auxiliary tone input a separate analog input to the loud speaker driver (audio interface #0) is provided for the purpose of sending auxiliary ringing/announcement tones to the loud speaker. this input (?auxtone?) allows analog signals to be buffered by the programmable-gain driver circuit. the auxtone path is not normally connected, and needs to be selected by the appropriate bits in the cross-point control register. the analog gain from auxtone to the speakerp/n pins is defined by the same register as for ?rx analog gain? in audio interface #0, and is adjustable between -26.5db and +5.9db in approximate steps of 2db. input impedance ? (kohms) gain min typ max 0db to 10.5db 49 107 213 12db to 22.5db 29 54 89 24db to 46.5db 52 80 113 ? these figures are for design aid only: not guaranteed and not subject to production testing.
mt92303 advance information 8 the maximum undistorted signal which can be generated by the speakerp/n pins has a ?peak? amplitude of approximately vdd-1 e.g. 2.3v peak, or 4.6v peak-peak, for a 3.3v supply. it should be noted that a combination of large input signal and maximum auxtone gain can cause the output signal to ?clip?. figure 7 - auxtone circuitry the auxtone input may be driven by a true analog source (e.g. op-amp) or a pseudo-analog signal provided by a ?digital? driver as shown in figure 7. for minimum external component count, the digital driver should go high-impedance when not in use (to minimize ?clicks? and ?pops?). the auxtone input is dc biased at vdd/2 and should be capacitively coupled to sources with a different dc level. cross-point any 2 of the 4 rx earpiece drivers may be selected for connection to the 2 codecs. similarly, any 2 of the 4 microphones may be selected for connection to the 2 codecs. this is done via the ?cross-point? and is controlled by the appropriate register. the same register contains two ?con_codec? bits which must be ?set? in order to establish any connection to the codecs. these bits allow the codecs to be completely disconnected from the audio interfaces (the default state after system reset). in the event of both codecs being erroneously selected for connection to one of the earpiece/microphone circuits, then codec #0 will take priority. in the event of one of the codecs being selected for connection to earpiece #0 (the driver designated for the loud speaker), and the simultaneous selection of the auxtone input, then the auxtone path will take priority. special cross-point modes the cross-point is normally used to setup one or two channels, each of which consists of a microphone circuit, a codec, and an rx earpiece driver. however, there are two special modes in which two earpiece drivers may be connected to the same codec (only codec #0). vdd gnd auxtone tri-state optional filtering digital buffer
advance information mt92303 9 these special ?dual output? modes are controlled by the ?override? bits in the ?cross-point: selection? register as shown in the following table. table 2 - special cross-point modes notice that one of the earpiece drivers is designated as ?master? when in ?dual output? mode. this means that the ?master? must also be selected for connection to codec #0 (by the other control bits in the ?cross-point: selection? register). electret bias programmable output voltages are available on three of the audio interfaces - these are provided for the biasing of electret microphones as shown in figure 8. figure 8 - programmable electret bias the electret bias is programmed via one of the control registers, and provides a stable, low noise voltage which is derived from the on-chip voltage-reference. the bias voltage is programmable from 0 to 2.5v (nominal) in 15 steps, and has a nominal output noise level of 25uv (rms, 300-3400hz). notice that almost all of the noise from the electret bias generator appears across the microphone. when the tx/mic gain is set towards its maximum value, the signal-to-noise performance will be affected by the noise from the bias generator. over ride cross-point operation 00 normal mode 01 auxtone to loud speaker output (ear #0). overrides xp0/1 10 dual output mode 1: ear#3 (master) and ear #0 connected to codec #0 11 dual output mode 2: ear#2 (master) and ear #3 connected to codec #0 micp micn micbias electret microphone programmable mic bias 0 to 2.5v in 15 steps 100n 100n gnd r1 r2
mt92303 advance information 10 microphone presence detect when an electret microphone is connected as shown in figure 8 and figure 9, it draws a bias current from the micbias pin. the voltage across the ?bottom? bias resistor is monitored by the micdetect input and is used to set a ?presence? flag in the mt92303?s status register. this allows the external controller to determine whether or not the handset and headset are plugged-in. the internal workings of the mt92303 are not affected by the state of the ?presence? flag. figure 9 - mic presence and mute detect microphone mute detect any of the 4 microphone inputs can be ?muted? under direct software control via the ?mode control? register. in addition, the micdetect inputs may also be used to mute the microphone paths of the 2 associated audio interfaces. this allows instantaneous blanking of the microphone path, and consequently the sidetone path, and allows the ?pop? associated with electret muting to be avoided. as shown in figure 9, the internal ?mic mute detect? signal is activated whenever the voltage across the ?bottom? bias resistor (r2) exceeds 40% of the micbias voltage. a small amount of hysteresis is implemented such that the voltage needs to fall below 35% of the micbias voltage before the internal ?mic mute detect? signal is deactivated. in addition to internally muting the microphone channel, the ?mic mute detect? signal is passed to the mt92303?s status register. micbias 0 to 2.5v in 15 steps gnd 40% 35% 4% 3% mic presence detect mic mute detect micdetect r1 r2
advance information mt92303 11 the behavior of the mute function can be programmed to operate in four different ways. table 3 - microphone mute detection it is important to note that in the third mode (mutemode=10) described in table3, it is the designer?s responsibility to re-enable the microphone path after it has been muted by the micdetect pin. this allows the designer to re-establish the signal path after a time sufficient for the settling of any microphone bias circuitry. the on-chip ?status? register provides access to the internal ?mic mute detect? signal, and also the acknowledged version ?mute? which denotes whether or not the microphone channel is actually muted. these two bits of information are expected to be used by the external controller to determine when the channel needs to be re-enabled. this will be when ?mute? is high, and ?mic mute detect? has fallen low, but the external controller may introduce a delay before re-establishing the microphone path. the path should be re-enabled by momentarily switching to mutemode=00. designation of audio interfaces as already described, the mt92303 has four audio interfaces which are very similar to each other. the following summary of the differences should be useful in the early stages of design, when the interfaces are being designated their specific tasks. ? mic #1 is the simplest interface, and has no electret bias facility, or microphone ?detect? circuitry. ? mic #0 has no microphone ?detect? circuitry. ? ear #0 has a higher drive capability, and may be used for a loud speaker. ? ear #0 may be connected to an ?external? signal via the auxtone pin. ? codec #0 may be used in special ?dual output? modes, but #1 may not. ? ear #3 and #0 may be driven simultaneously by the same signal (codec #0) in a special ?dual output? mode. ? ear #2 and #3 may be driven simultaneously by the same signal (codec #0) in a special ?dual output? mode. bandgap voltage reference the mt92303 has its own internal bandgap voltage reference which determines the absolute gains of the tx & rx paths. the bandgap voltage is brought out to the vref pin for external decoupling with a capacitor (100nf to gnda) that should be located as close to the package as possible. the bandgap voltage has a nominal value of 1.26v and may be used by other external circuitry as long as this is not allowed to interfere with the reference voltage. the reference voltage is not designed to deliver current so it should not be connected to a resistive load, or an ac noise source which cannot be decoupled by the external capacitor alone. the reference voltage circuit may be powered up and down under the control of one of the internal registers. when it is powered up, the reference voltage will take <1ms to settle. mute mode mute operation (see figure 9) 00 microphone path enabled (normal operation). ?mic mute detect? signal ignored. 01 microphone path disabled (muted) while ?mic mute detect? signal is high, and enabled while low. 10 microphone path disabled (muted) while ?mic mute detect? signal is high, but must be re-enabled by the external controller . 11 microphone path disabled (muted). ?mic mute detect? signal ignored.
mt92303 advance information 12 pcm interface (voice & status) the tx and rx digitized voice data is accessed via the pcm interface which can be programmed to work in one of three modes. these are st-bus, gci and ssi mode as described below. the contents of an on-chip ?status? register may also be read via this interface.the dsto/dout/sdt pin is high impedance when inactive - this allows multiple codecs to share the pcm bus. table 4 - pcm interface pin description pcm codes which are equivalent to a ?digital mw? (0dbm0) for a 1khz sinewave are shown in table5. itu-t g.711 defines the peak coding level for a-law as 3.14dbm0 and for u-law as 3.17dbm0. table 5 - pcm coding the a-law and u-law schemes use sign-magnitude data, and the linear system uses 2?s compliment. the data words are shown as msb first. table5 also shows the coding for full-scale and ?zero? (?quiet code?). pin name type description c4i /dcl/sck input serial clock. st-bus = 4.096mhz gci = 1.536 - 4.096mhz ssi = 0.512 - 4.096mhz f0i /fsc/sc2 input frame alignment. st-bus active low pulse gci active high pulse ssi active high dsti/d in /srd input serial data dsto/d out /std output serial data phase a-law u-law linear -7/8 00110100 00011110 1101110110000100 -5/8 00100001 00001011 1010111010000100 -3/8 00100001 00001011 1010111010000100 -1/8 00110100 00011110 1101110110000100 1/8 10110100 10011110 0010001001111100 3/8 10100001 10001011 0101000101111100 5/8 10100001 10001011 0101000101111100 7/8 10110100 10011110 0010001001111100 -full 00101010 00000000 1000000000000000 zero 11010101 11111111 0000000000000000 +full 10101010 10000000 0111111111111111
advance information mt92303 13 pcm st-bus interface the st-bus consists of output (dsto) and input (dsti) serial data streams, a synchronous clock input signal ( c4i ), and a framing pulse input ( f0i ). these are shown in figure 10. the data streams operate at 2048 kb/s and are time division multiplexed into 32 identical channels of 64 kb/s bandwidth. a frame pulse (a 244 nsec low going pulse) is used to parse the continuous serial data streams into the 32 channel tdm frames. each frame has a 125 usecond period translating into an 8 khz frame rate. data is arranged msb first. a valid frame begins when f0i is logic low coincident with a falling edge of c4i . refer to mitel applications note msan-126 for detailed st-bus timing. c4i has a frequency (4096 khz) which is twice the data rate. this clock samples the incoming data on dsti at the 3/4 bit-cell position (the second rising clock edge) and makes data available on dsto at the start of the bit-cell. a bit cell is the 2 clock cycles used to transfer 1 data bit. see figure 17 in the electrical characteristics section for detailed timing information. figure 10 - pcm st-bus channel allocation in a frame pulse channel definition (st) each codec requires 1 (companded pcm) or 2 (linear pcm) channels. in addition to these 2 or 4 channels there is a ?status? channel. the allocation of these channels is fully programmable, subject to the following: ? data-in and data-out are in the same channel slot for the dsti and dsto streams. ? in 16bit linear mode the 2 bytes are in adjacent channels. this will allow multiple mt92303s to share the st-bus (10 in companded and 6 in linear mode). in the event of the codecs or the status register erroneously having the same channel allocation, the prioritisation is (highest first): codec0, codec1, status. only the highest priority has access to the pcm channel. 125us 32 st-bus channels c4i = 4096khz f0i c4i dsti/dsto ch 15 ch 14 ch 13 ch 12 ch 11 ch 10 ch 9 ch 8 ch 23 ch 22 ch 21 ch 20 ch 19 ch 18 ch 17 ch 16 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 ch 31 ch 30 ch 29 ch 28 ch 27 ch 26 ch 25 ch 24 bit 7 3.90625us 1 channel c4i = 4096khz c4i bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dsti/dsto
mt92303 advance information 14 pcm general circuit interface (gci) in gci mode the number of channels available in a 125us frame pulse period depends on the dcl clock frequency, a dcl clock frequency of 1536khz allows 3 channels, 2048khz allows 4 channels and 4096khz allows 8 channels. each channel is allocated 4 consecutive bytes which are defined as: ? pcm data bytes b1 and b2. ? monitor byte (m). ? control/indication byte (c/i). for the mt92303 only the b1 and b2 bytes are used, during the m and c/i bytes, dout is tristate. the serial data streams are din and dout, the clock is dcl and the frame pulse is fsc, as shown in figure 11. data is arranged msb first. the channels selected must be compatible with the dcl clock frequency being used. the ?status? register information is also output on one other channel, in the b1 slot. gci mode is enabled by setting the appropriate bits in the control register. the clock rate for gci is double the bit rate. see figure 18 in the electrical characteristics section for detailed timing information. channel definition (gci) the pcm data will be output on the channels defined by the channel allocation registers. the status register is also output on one other channel on b1 as defined by the status channel allocation register. no error checking is done so the channels defined must be compatible with the dcl clock frequency. in the event of codecs or status reg. erroneously having the same channel allocation, the prioritisation is (highest first): codec0, codec1, status. only the highest priority has access to the pcm channel. figure 11 - pcm gci channel allocation in a frame pulse fsc dcl d in /d out b2 b1 b1 b1 b1 b1 b1 b1 b1 m c/i 125us 8 gci channels dcl = 4096khz d in /d out dcl ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 15.625us 1 channel dcl = 4096khz
advance information mt92303 15 pcm synchronous serial interface (ssi) this is a commonly used standard in north america. there is no predefined number of bits in a 125us period, instead data is transmitted while the serial chip select pin sc2 is high. data is input on sdr, being sampled on the falling edge of sck, data is output on sdt on the rising edge of sck. data is arranged msb first. the clock rate for ssi is the same as the bit rate. see figure 19 in the electrical characteristics section for detailed timing information. figure 12 - pcm synchronous serial interface (ssi) channel definition (ssi) in dual codec mode, codec0 data is transmitted first, either as 8-bit companded or 16-bit linear, then codec1 data and finally the status register. in single codec mode, the codec data is transmitted first and then the status register. figure 13 - pcm ssi bit allocation sc2 sck sdr sdt 125us data data sc2 sck sdr b2 sdt b1 b2 b1 b2 b1 codec 0 codec 1 b2 b1 status sdr sdt b1 b1 codec 1 status codec 0 disabled, codec 1 companded codec 0 and 1 enabled, both 16-bit linear sc2
mt92303 advance information 16 serial microport all mt92303 internal registers are accessed for write via the serial microport to allow programming of the device. in addition some registers may be read via this interface as defined in the ?programming and registers? section. table 6 - microport pin description the serial microport is compatible with motorola spi (cpol=0, cpha=0), and national semiconductor microwire specifications. functional waveforms are shown in and figure 14. detailed timing diagrams are shown in figure 19 and figure 20 in the electrical characteristics section. the microport consists of a transmit/receive data pin (data1), a receive data pin (data2), a chip select pin ( cs ) and a synchronous data clock pin (sclk). receive data bits are sampled on the rising edge of sclk while transmit data is clocked out on the falling edge of sclk. the mt92303 supports motorola half-duplex processor mode (cpol=0 and cpha=0). this means that during a write to the mt92303 by the motorola-type processor, output data from the data1 pin must be ignored (by the processor). this also means that input data on the data2 pin is ignored by the mt92303 during a valid read by the motorola processor. all data transfers through the microport are two bytes long. this requires the transmission of a command/address byte followed by the data byte to be written to or read from the addressed register. cs must remain low for the duration of this two-byte transfer. as shown in and figure 14 the falling edge of cs indicates to the mt92303 that a microport transfer is about to begin. the first 8 clock cycles of sclk after the falling edge of cs are always used to receive the command/ address byte from the microcontroller. the command/address byte contains information detailing whether the second byte transfer will be a read or a write operation (read = 1, write = 0), and at what address. the next 8 clock cycles are used to transfer the data byte between the mt92303 and the microcontroller. at the end of the two-byte transfer, cs is brought high again to terminate the session. the rising edge of cs will tri- state the data1 pin. the data1 pin will remain tri-stated as long as cs is high. motorola/national processors use most significant bit (msb) first transmission. pin name type description cs input enables serial microport. active low. rising edge completes the cycle. sclk input data clock for serial microport data1 output motorola/national mode: data1 is output. data2 input motorola/national mode: data2 is input.
advance information mt92303 17 figure 14 - microport waveform (motorola/national mode) microport timing requirements as shown in and figure 20, there are several ?sequencing? requirements which must be met. the sclk edges must not start until cs is active (low), and must complete before it is taken inactive (high). there are setup and hold time requirements between the data and sclk signals. piping into the dsp/codec registers the mt92303 has a total of 25 internal registers which are written to via the serial microport. these are split into two groups which need to be accessed in different ways. most of the registers (0ah to 19h) are directly accessed by the microport. the other 10 (00h to09h), which are associated with the internal dsp/codec engines, have their data temporarily ?buffered? by the microport, after which it needs to be piped into its final destination. this requires an extra 18 sclk cycles which may be provided in several different ways as described in the following list and as shown in figure 15. a: this is the ?normal? microport operation for a ?non-dsp? register - 16 sclk cycles are required. b: this is the simplest way to write to a ?dsp/codec? register - it requires 16+18 sclk cycles per operation. alternatively, sclk may be allowed to run continuously rather than in bursts. c: the extra sclk cycles required for the ?dsp/codec? write are provided by two further microport operations - notice that cs is not active for these. one method of achieving this is to arrange for the microport controller to write/read to another (non existent) peripheral i.e. not the mt92303. in this way, the sclk cycles will be generated, but the mt92303 will not be ?selected?. d: the required sclk cycles are provided by performing a ?triple write? to each ?dsp/codec? register. e: the required sclk cycles are provided by performing a triple operation to each ?dsp/codec? register. in this case, the two extra operations are ?reads? from the non existent register ?3f?. f: this method allows the programming to be carried out in fewer operations than the ?triple operations? described above. each ?dsp/codec? register is written-to twice, but it is important to notice that the sequence must end with a read/write operation to a ?non-dsp? register. rd a5 a4 a3 a2 a1 a0 x d7 d6 d5 d4 d3 d2 d1 d0 cs sclk data1 output x x x x x x x x data2 input command/address data read wr a5 a4 a3 a2 a1 a0 x data1 output data2 input write d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x
mt92303 advance information 18 g: this method allows the programming to be carried out in the minimum number of operations, but is more complicated. each ?dsp/codec? register is written-to with a single operation, but notice that there is a sequencing requirement. the operations must alternate between the registers for dsp/codec #0 and #1. in addition, the last ?dsp/codec? operation must be followed by two read/write operations to a ?non-dsp? register. figure 15 - options for writing to the dsp/codec register cs sclk data data ignored data ignored read from 3f read from 3f repeat-write repeat-write write dsp write dsp #0 write non-dsp repeat-write write dsp #1 repeat-write write dsp #0 2 x write non-dsp write dsp #1 write dsp #0 write dsp #1 write non-dsp write dsp write dsp write dsp a. b. c. d. e. f. g . cs sclk data cs sclk data cs sclk data cs sclk data cs sclk data cs sclk data
advance information mt92303 19 system clock the mt92303 requires a ?system? clock signal which is used to run the internal dsp circuitry. the mt92303 is designed to work with several popular clock frequencies as shown in table7. the ?system? clock should be presented to the ?sysclk? input (standard digital input), and the appropriate on-chip register should be programmed with the chosen frequency. table 7 - sysclk frequencies only the frequencies shown in table7 may be used - this is a requirement of the internal dac?s and adc?s which are of the ?over-sampling? type. the sysclk frequency needs to be a multiple of the 8khz frame rate, and also the internal sampling clocks of the dac?s and the adc?s. some of the sysclk frequency options use an internal pll to multiply the clock up to 20.48mhz, but the faster sysclk frequencies are used directly by the dsp circuitry. when ?direct? sysclk frequencies are used, the clock signal must have a mark-to-space ratio between 40:60 and 60:40. figure 16 - sysclk input and pll those sysclk frequencies which are multiples of 2.048mhz are expected to be derived from the same source as that which provides the pcm interface?s ?frame alignment? signal ( f0i /fsc/sc2) . the two signals must be synchronous - one of the ways that this can be achieved is by using the same clock signal for both sysclk and c4i /dcl/sck. the other sysclk frequencies are intended for use in voip applications where ethernet clocks may already be available. the mt92303 contains a digital re-synchronization circuit which means that the 20.0, 25.0 or 50.0mhz sysclk does not need to be synchronous with the ?frame alignment? signal. however, in these cases, there are minimum requirements for the accuracy of the 8khz ?frame alignment? frequency, as shown in table7. system clock mhz clocking method required frame alignment frequency 20.48 direct 8khz, synchronous 20.0 direct 8khz +/-400ppm 25.0 direct 8khz +/-320ppm 50.0 direct 8khz +/-320ppm 2.048 internal pll 8khz, synchronous 4.096 internal pll 8khz, synchronous 10.24 internal pll 8khz, synchronous sysclk pll 20.48 mhz internal clock enable
mt92303 advance information 20 it is important to note that the accuracy figures in table7 (e.g. 8khz +/-320ppm for 25mhz system clock) are defining the relative inaccuracy of the two clocks (8khz and 25mhz in this example). the two clock frequencies must share the 320ppm of allowable inaccuracy (e.g. 8khz +/-160ppm and 25mhz +/-160ppm). the internal pll must be enabled whenever it is required. this is controlled by the same register as is used to select the sysclk frequency. the pll will take <1ms to lock onto the sysclk signal - during this time the ?dsp? circuitry will be clocked at the wrong frequency (slower, or faster), and consequently the pcm data should not be relied upon until the pll has settled. when the pll is not needed, or when a ?low power? mode is required, then the pll should be disabled. the pll should not be enabled until the sysclk clock signal has been applied. it is acceptable to simultaneously select the sysclk frequency and enable the pll. after a system reset, the mt92303 will be in a ?direct? clocking mode (20.48mhz direct as shown in table7), and consequently must be put into a mode where the pll is programmed to multiply the sysclk frequency by the correct amount, and where the pll is ?enabled? (if the pll is required). system reset options the mt92303 has a ?reset? mode in which all the control registers, the dsp, and all other latched functions are ?reset?. this ?reset? mode may be initiated in three different ways: ? powering-up the device ? using the active-low ?resetb? pin ? setting the ?sw_reset? bit in the appropriate register the ?software? reset is programmed via the microport interface, and is cleared by another dummy microport operation. this must be a ?read? operation from register address 3f (a non-existent register). power-down mode the individual circuits of the mt92303 are capable of being powered-down when not needed. this allows the operating current to be minimized, and it also allows the whole chip to be powered-down into a micro-power state if required. the circuits are powered-down under the control of the relevant register bits. in general, the circuitry is powered-down after a power-on-reset or hardware or software reset, and is usually ?enabled? when required. to put the mt92303 into micro-power mode, all of the circuits listed below need to be ?disabled? by setting the register bits low. for absolute minimum power consumption, the system clock must also be stopped. ? audio interfaces #0 to #3 (?en_audio? x4) ? tx analog #0 and #1 (?en_tx? x2) ? voltage reference (?en_vref? x1) ? pll (?en_pll? x1) ? codecs #0 and #1 (?en_codec? x2)
advance information mt92303 21 mt92303 programming & registers all operating modes, power up/down, gain levels and muting, electret biasing, filter cut-off?s etc. are set by the contents of the registers shown below. these are all accessed via the microport. some of the registers are write-only, some are read-write, and the ?status? register is read-only. the ?hex? addresses and read/write access are shown at the top of each table. note that most of the registers are duplicated - there are generally 2 addresses for registers which control the codecs and 4 addresses for those which control the audio interfaces. register defaults the mt92303 has an on-chip ?power on reset? circuit which is used to clear and initialize the circuitry whenever power is applied to the device. the resetb pin may also be used to provide a ?hardware? reset which produces the same effect. in this state, all the register bits are reset to ?0? figure 21 shows a flow diagram with a suggested register programming sequence. there are several ?sequencing? requirements shown in the flow diagram - it is important that these are followed. table 8 - dsp rx volume control address 00h/01h write only dsp/codec: control (registers x2) 0 mute_v ?dsp? rx mute 1 mute_s ?dsp? sidetone mute 2 pcm 0=linear 1=companded 3 u/a law 0=a law 1=u law 4-7 - unused (don?t care) address 02h/03h write only dsp/codec: enable and rx dsp gain (registers x2) 0 en_codec enable codec 1 vol[0] ?dsp? rx volume control from -21db to 0db in 3db steps. see table below 2 vol[1] 3 vol[2] 4-7 - unused (don?t care) vol[2:0] gain db 000 0 001 -3 010 -6 011 -9 100 -12 101 -15 110 -18 111 -21
mt92303 advance information 22 table 9 - rx path dsp hi pass filter table 10 - sidetone gain address 04h/05h write only dsp/codec: rx hi-pass-filter (registers x2) 0 rxhpf[0] cut off frequency of rx path ?dsp? hi pass filter (1 st order filter). see table below 1 rxhpf[1] 2 rxhpf[2] 3 scan[0] scan-path test modes. (defaults to ?00?. do not over-write with different value) 4 scan[1] 5-7 - unused (don?t care) rxhfp[2:0] -3db frequency (hz) 000 0 001 40 010 100 011 150 100 200 101 300 110 400 111 invalid address 06h/07h write only dsp/codec: sidetone gain (registers x2) 0 dsp test dsp bus access test mode. (defaults to ?0?. do not over-write with different value) 1 stg[0] sidetone gain. see table below 2 stg[1] 3 stg[2] 4 stg[3] 5-7 - unused (don?t care) stg[3:0] gain (db) stg[3:0] gain (db) 0000 -39 1000 -15 0001 -36 1001 -12 0010 -33 1010 -9 0011 -30 1011 -6 0100 -27 1100 -3 0101 -24 1101 0 0110 -21 1110 +3 0111 -18 1111 +6
advance information mt92303 23 table 11 - tx path analog gain address 08h/09h write only dsp/codec: dsp test (registers x2) 0 dsptest[0] reserved (defaults to ?0?. do not over-write with different value) 1 dsptest[1] reserved (defaults to ?0?. do not over-write with different value) 2 dsptest[2] reserved (defaults to ?0?. do not over-write with different value) 3-7 - unused (don?t care) address 0ah - 0bh read/write audio interface: tx gain (registers x2) 0 txg[0] programmable tx gain 0 to +46.5db in 1.5db steps. see table below txg[4] controls whether or not the ?pre-amp? is used 1 txg[1] 2 txg[2] 3 txg[3] 4 txg[4] 5-7 - unused (don?t care) txg[4:0] gain db txg[4:0] gain db txg[4:0] gain db txg[4:0] gain db 00000 0 01000 12 10000 24 11000 36 00001 1.5 01001 13.5 10001 25.5 11001 37.5 00010 3 01010 15 10010 27 11010 39 00011 4.5 01011 16.5 10011 28.5 11011 40.5 00100 6 01100 18 10100 30 11100 42 00101 7.5 01101 19.5 10101 31.5 11101 43.5 00110 9 01110 21 10110 33 11110 45 00111 10.5 01111 22.5 10111 34.5 11111 46.5 address 0ch - 0fh read/write audio interface: rx analog gain and electret bias (registers x4) 0 rxg[0] programmable rx ?analog? gain -28db to +2.0db in 2db steps (available for all four audio interfaces). see table below register for audio interface #0 also defines ?auxtone? gain between -26.5db and +5.9db in approximate 2db steps. see table below 1 rxg[1] 2 rxg[2] 3 rxg[3] 4 eb[0] programmable electret microphone bias 0v to 2.5v in 163mv steps. see table below available for audio interfaces #3, #2 and #0 5 eb[1] 6 eb[2] 7 eb[3]
mt92303 advance information 24 table 12 - rx ?analog? gain table 13 - #0 auxtone gain table 14 - electret bias rxg [3:0] gain (db) rxg [3:0] gain (db) 0000 -28 1000 -12 0001 -26 1001 -10 0010 -24 1010 -8 0011 -22 1011 -6 0100 -20 1100 -4 0101 -18 1101 -2 0110 -16 1110 0 0111 -14 1111 +2 rxg0 [3:0] aux gain (db) rxg0 [3:0] auxgain (db) 0000 -26.5 1000 -10.1 0001 -24.5 1001 -7.9 0010 -22.5 1010 -5.8 0011 -20.4 1011 -3.6 0100 -18.4 1100 -1.4 0101 -16.3 1101 +1.0 0110 -14.2 1110 +3.4 0111 -12.2 1111 +5.9 eb [3:0] bias v eb [3:0] bias v 0000 0.04 1000 1.34 0001 0.21 1001 1.51 0010 0.37 1010 1.67 0011 0.53 1011 1.84 0100 0.69 1100 2.00 0101 0.85 1101 2.16 0110 1.02 1110 2.32 0111 1.18 1111 2.49
advance information mt92303 25 address 10h read/write audio interface: enable (register x1) 0 en_audio_0 enable audio interfaces (rx ?analog? circuitry, electret bias, microphone detect, auxtone) 1 en_audio_1 2 en_audio_2 3 en_audio_3 4 en_vref enable voltage reference (needed for all analog functions) 5 en_tx0 enable tx ?analog? circuitry. also initiates the ?tx offset correction? routine. important note : there are several requirements which must be met before this routine can operate correctly. see explanation in section ? automatic dc offset cancellation (tx) ? 6 en_tx1 7 - unused (don?t care) address 12h/13h read/write pcm interface: codec channel allocation (register x2) 0 chan[0] codec-channel allocation st-bus mode: (0 to 31) e.g. chan[4:0] = 01110 = channel 14 gci mode: (0 to 7) e.g. chan[4:0] = xx110 = channel 6 ssi mode: ignored 1 chan[1] 2 chan[2] 3 chan[3] 4 chan[4] 5-7 - unused (don?t care) address 14h read/write pcm interface: status channel allocation (register x1) 0 chan[0] status-channel allocation st-bus mode: (0 to 31) e.g. chan[4:0] = 01110 = channel 14 gci mode: (0 to 7) e.g. chan[4:0] = xx110 = channel 6 ssi mode: ignored 1 chan[1] 2 chan[2] 3 chan[3] 4 chan[4] 5-7 - unused (don?t care) address 15h read/write general: mode control (register x1) 0 pcm_bus[0] selects pcm data interface 00 = st-bus, 01 = gci, 10 = ssi 1 pcm_bus[1] 2 mutemode3[0] audio interface #3: mic mute mode control (see section ?microphone mute detect? and table below) 3 mutemode3[1] 4 mutemode2[0] audio interface #2: mic mute mode control (see section ?microphone mute detect? and table below) 5 mutemode2[1] 6 mute[0] software mute for audio interface #0 7 mute[1] software mute for audio interface #1
mt92303 advance information 26 table 15 - mute modes table 16 - system clock frequencies mutemode[1:0] mute operation (see figure 9) 00 microphone path enabled (normal operation). ?mic mute detect? signal ignored 01 microphone path disabled (muted) while ?mic mute detect? signal is high, and enabled while low 10 microphone path disabled (muted) while ?mic mute detect? signal is high, but must be re- enabled by the external controller 11 microphone path disabled (muted). ?mic mute detect? signal ignored address 16h read/write general: system clock frequency, pll and software reset (register x1) 0 freq[0] system clock frequency, ?sysclk?. see table below note : some frequencies need the internal pll to be enabled 1 freq[1] 2 freq[2] 3 en_pll enable pll (only required for some sysclk frequencies). allow 1ms to settle 4 sw_reset ?software reset? - see explanation in section ?system reset options? 5-7 - unused (don?t care) freq [2:0] system clock (mhz) clocking method pll multiplier 000 20.48 direct (pll output not used) x10 001 20.0 direct (pll output not used) x5 010 25.0 direct (pll output not used) x2 011 50.0 direct (pll output not used) x2 100 2.048 internal pll x10 101 4.096 internal pll x5 110 10.24 internal pll x2 111 10.24 (spare) internal pll x2 address 17h read/write general: test (register x1) ? 0 test[1:0] reserved ? for ?gemulation mode? testing 1 2 test[3:2] reserved ? for internal signal testing via dtso pin. 01 = internal sysclk (pll output in some modes) 3 4 0 reserved ? 5 0 6 0 7 0 ? defaults to all-zero?s. do not over-write with different values
advance information mt92303 27 address 18h read/write general: test tx analog (register x1) ? 0 pdvc reserved ? for production testing 1 pdsd 2 pddac 3 tcalvg 4 tcalma 5 tstvg 6 tstaa 7 - address 19h read only audio interface: status (register x1) 0 mutedet3 audio interface #3: ?mic mute detect? signal 1 mute3 audio interface #3: microphone channel is muted (may need to be actively un-muted) 2 mutedet2 audio interface #2: ?mic mute detect? signal 3 mute2 audio interface #2: microphone channel is muted (may need to be actively un-muted) 4 mic3 audio interface #3: ?mic presence detect? signal 5 mic2 audio interface #2: ?mic presence detect? signal 6-7 - unused (don?t care)
mt92303 advance information 28 ac/dc electrical characteristics ? exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings ? characteristics min max units comments storage temperature -55 +150 degc supply voltage -0.3 5.0 v < 2 minutes -0.3 3.6 v continuous pin voltage relative to vdd +0.3 v pin voltage relative to gnd or sub -0.3 v recommended operating conditions characteristics min max units comments ambient temperature -40 +85 c supply voltage vdd 3.0 3.6 v general characteristics characteristics min typ ? max units comments supply current 13 23 ma operating. no output loads 10 ua powered down digital inputs: lower threshold 0.8 v digital inputs: upper threshold 2.0 v digital outputs: lower level 0.4 v sinking 6ma digital outputs: upper level 0.8*vdd sourcing 6ma rx path characteristics all parameters are measured differentially between the ?earp? and ?earn? pins. dsp gain is set to 0db unless otherwise stated. characteristics min typ ? max units comments output level for 0dbm0 0.83 0.90 0.97 v rms analog gain set to 0db 35.8 mv rms analog gain set to -28db driver output power 66 mw rms 1khz sinewave, <1% thd, 32 ohm load speaker output power (audio interface #0 only) 150 mw rms 1khz sinewave, <1% thd, 16 ohm load output resistance 1 ohms 1khz sinewave analog gains -28 to +2 db 16 gain values available analog gain error -1.0 0 +1.0 db analog gain -28db to +2db, 1khz, 0dbm0 analog gain step size 2 db idle channel noise -68 dbm0p u/a law mode. analog gain set to 0db -68 linear mode. analog gain set to 0db dc offset voltage -50 +50 mv analog gain 0db ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing.
advance information mt92303 29 * typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. auxtone path characteristics all parameters are measured differentially between the ?ear0p/speakerp? and ?ear0n/speakern? pins unless otherwise stated. characteristics min typ ? max units comments gain -26.5 to +5.9 db 16 gain values available gain step size 2 db step sizes not all equal maximum gain setting -0.5 5.9 +0.5 db 1khz, 1v rms sinewave input dc bias vdd/2 v auxtone input auxtone input resistance (ac) 83 kohms minimum gain setting 29 kohms maximum gain setting tx path characteristics all parameters are referred to the differential signal between the ?micp? and ?micn? pins unless otherwise stated. characteristics min typ ? max units comments input level for 0dbm0 0.56 0.611 0.67 v rms gain set to 0db 2.89 mv rms gain set to 46.5db input common-mode bias vdd/2 v dc bias on each input, relative to gnd input resistance (ac) 107 kohms gain 0db to 10.5db 54 kohms gain 12db to 22.5db 80 kohms gain 24db to 46.5db gains 0 to +46.5 db 32 gain values available gain error -0.75 0 +0.75 db gain 0db to 46.5db, 1khz, 0dbm0 gain step size 1.5 db idle channel, output noise -77 dbm0 output noise. gain set to 0db -53 dbm0 output noise. gain set to 46.5db
mt92303 advance information 30 ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. electret bias, mic presence and mic mute detect characteristics all parameters measured at the ?micbias? pin relative to gnd. characteristics min typ ? max units comments electret bias voltage ?ebv? 0.9 * typ - 50mv 0.04 to 2.49 1.1 * typ + 50mv v 16 levels available. see registers 0c-0f output noise 25 uv rms 300-3400hz drive current capability 1 ma source current output resistance 2 ohms at 1khz supply rejection 60 db at 1khz ?presence? detect threshold (rising) typ - 20mv 0.04 * ebv typ + 20mv v derived from electret bias voltage ?presence? detect threshold (falling) 0.03 * ebv ?mute? detect threshold (rising) 0.97 * typ - 10mv 0.40 * ebv 1.03* typ + 10mv v derived from electret bias voltage ?mute? detect threshold (falling) 0.35 * ebv
advance information mt92303 31 figure 17 - pcm st-bus data port timing pcm serial data interface timings (st-bus) characteristics sym min typ max units test notes c4i period t c4p 243.9 244.1 244.4 ns c4i /dcl/sck clock high t sch, t c4h 90 ns c4i /dcl/sck clock low t scl, t c4l 90 ns f0i / fsc setup t f0is 20 150 ns f0i / fsc hold t f0ih 20 150 ns st-bus/gci data input hold time t dsh 20 ns st-bus/gci data input setup time t dss 20 ns st-bus/gci data output delay t dsd 80 ns c l =150pf st-bus/gci output active to high impedance t ashz 80 ns c l =150pf dsto v t c4i v t f0i v t dsti v t t f0is t f0ih t dss t dsh t dsd t ashz t c4h t c4l bit 6 bit 7 bit 6 start of frame bit 7
mt92303 advance information 32 figure 18 - pcm gci data port timing pcm serial data interface timings (gci) characteristics sym min typ max units test notes dcl period t ckp 244 651 ns c4i /dcl/sck clock high t sch, t c4h 90 ns c4i /dcl/sck clock low t scl, t c4l 90 ns f0i / fsc setup t f0is 20 150 ns f0i / fsc hold t f0ih 20 150 ns st-bus/gci data input hold time t dsh 20 ns st-bus/gci data input setup time t dss 20 ns gci fsc to data delay (first bit) t sd 80 ns c l =150pf st-bus/gci data output delay t dsd 80 ns c l =150pf st-bus/gci output active to high impedance t ashz 80 ns c l =150pf dout v t dcl v t fsc v t din v t t f0is t f0ih t dss t dsh t dsd t ashz t c4h t c4l bit 7 bit 6 bit 7 bit 6 start of frame t sd
advance information mt92303 33 figure 19 - pcm ssi data port timing pcm serial data interface timings (ssi) characteristics sym min typ max units test notes sck period t scp 244 1953 ns c4i /dcl/sck clock high t sch, t c4h 90 ns c4i /dcl/sck clock low t scl, t c4l 90 ns ssi enable strobe to data delay (first bit) t sd 80 ns c l =150pf ssi data output delay (excluding first bit) t dd 80 ns c l =150pf ssi output active to high impedance t ahz 80 ns c l =150pf ssi enable strobe signal setup t ss 70 t scp ns ssi enable strobe signal hold t sh 15 t scp -10 ns ssi data input setup t sds 10 ns ssi data input hold t sdh 15 ns sdt v t sck sc2 v t sdr v t t ss t sh t sds t sdh t dd t ahz t scl t sch bit 7 bit 6 bit 7 bit 6 t scp v t start of frame t sd
mt92303 advance information 34 figure 20 - motorola/national serial microport timing microport timings characteristics sym min typ max units test notes input data setup t ids 100 ns input data hold t idh 30 ns output data delay t odd 100 ns c l =150pf serial clock period t scp 500 ns sclk pulse width high t sch 250 ns sclk pulse width low t scl 250 ns cs setup-motorola t cssm 100 ns cs hold t csh 100 ns cs to output high impedance t ohz 100 ns c l =150pf data2 sclk cs data1 t ids t idh t odd t cssm t csh t ohz t sch t scl t scp (input) (output)
advance information mt92303 35 figure 21 - suggested microport programming sequence power-on reset or hardware reset - ?resetb? or software reset - write addr 16h enable vref - write addr 10h wait 1ms for vref to settle set mode - write addr 15h set system clock frequency program codec 0/1 - write addr 00-07h set tx gains - write addr 0a-0bh ** run f0i clock for 128 periods (16ms) for tx offset cancellation set rx gains & electret bias - write addr 0c-0fh set pcm & status channel - write addr 12-14h enable codec 0/1 - write addr 02-03h * enable tx 0/1 and audio 0-3 - write addr 10h set cross-point - write addr 11h talk wait 1ms for pll to settle (if used) *** **** and enable pll (if required) - write addr 16h **** after a frequency register write, each codec must be enabled or re-enabled. tx 0/1 must be enabled after vref has settled. sysclk must be present before pll is enabled. **** * *** enable codec 0/1 - write addr 02-03h ** c4i_ must be running during tx offset cancellation.

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